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device description the l6353 is a smart silicon device which integrates all the circuitry for a versatile and rugged gate driver. the chip implements several features such as: an easy-to-link signal source by means of either an optocoupler or pulse transformer, a two-step turn-on procedure of the external power switch (dedi- cated to igbt driving), a switch dropout voltage monitoring, the possibility to give a negative bias to the gate, the external programmability of safety thresholds and delays, the syncronisation and edge aligning and a powerful buffer of 8a with split output. to introduce the device see fig.1 which shows the functional diagram: AN556/0497 AN556 application note the l6353: a smart gate driver by: c. adragna and g. comandatore the superior performance of voltage controlled switch makes this device the preferred one in modern power electronics applications. the l6353 is a new monolithic integrated circuit designed to realise a versatile and smart interface between the signal circuitry and every kind of voltage controlled power switch, with a minimal design time and a reduction of parts count. 1.25v 2.5v 300 ma + - + - filter 200ns 1.25v 3.75v ref + - 3.15v thermal shutdown select input inv-out alarm delay com supply uv lockout references out2 vss von-sense on-lev-prog + - 7.5v clamp-prog out1 clamping mon-delay 3.15v 3.75v - + - + logic vpos out1 figure 1. l6353 - functional diagram 1/16
functional description interfacing l6353 to the signal source a typical switching application requires a good noise immunity on the incoming signal to avoid the switch false triggering (turn-on/turn-off). besides, electrical isolation and level shifting between the power and the signal parts can be needed. the l6353 is designed with the reference thresholds of control signal at 3.75v on rising edge and 1.25v on falling-edge (compatible with the cmos output-levels), a fixed 200ns analog filter to eliminate glitches and some tricks to ease linking to the signal source. figures 2, 3 and 4 sketch some practicable circuits and show the main signals. fig.2 shows the direct feeding of control signal to the input pin. the gate is driven in-phase by leaving the select pin ats 2.5v (the phase is reversed if the pin is grounded). in applications requiring electrical isolation, the select pin is designed especially for biasing a pulse transformer. then, the quiescent level at input pin is shifted to 2.5v and there is a differential threshold of +1.25v at switch-on and -1.25v at switch off. a cheap way to get the electrical isolation resorts to an optocoupler. in this case, the built-in 5v at vref pin can be used to bias the optocoupler and, of course, the select pin allows to manage the phase. figure 2. direct interfacing and main waveforms. 1 .25 v 2.5 v 300ma filter 20 0ns 1 .25v supp ly uv lockou t refere nces power & co ntr ol 3.75 v + - out1 com out2 v gate re f input 1 00nf 10 0nf s el ect source + - figure 3. pulse-transformer interfacing and main waveforms. com vgate 47 w 100nf source select input ref 1.25v 2.5v 300 m a filter 200ns 1.25v supply uv lockout references power & control + - 3.75v out1 out2 + - 100nf AN556 application note 2/16
failure warning at the alarm output the l6353 sends an alarm signal in case of fault detection either in the chip or in the driven switch. the system monitors chip temperature, chip supply voltage and the switch voltage drop in on state. the fault signal, available at alarm pin, is active low. the totem-pole output, with + 20ma current capability, is also useful (see fig.5) to get a signal either high or low on fault. synchronising more switches often, more switches must work synchronously. the synchronisation is always guaranteed by using the signal at output instead of the one at input, because of the l6353 safe processing. the inv-out pin is suitable for this function (see fig.6) because it sends a signal out of phase with the output, with + 20ma of current capability. s ele ct input 100nf 4.7k w ref 1.25v 2.5v 300 m a filter 200ns 1.25v s upply uv lockout references power & control + - 3.75v o ut1 v gate source 470 w out2 com + - figure 5. alarm circuitry and waveforms on power-on. figure 4. optocoupler interfacing and main waveforms. out1 com out2 vdrop-switch on-sense input power & control vcc alarm active-low 4.7k w 4.7k w active-high positive supply 100m f iload supply uv lockout references thermal shutdown AN556 application note 3/16
aligning the switching edges in inverter leg applications the difference in response time of each switch can lead to simultaneous con- duction. an easy way to align the switch edges is to place an adequate delay in the signal path of each driver. the l6353 is provided with the delay pin to adjust the input-to-out1 lag at turn-on by means of an rc cell connected to the ref pin (see fig.7). com supply uv lockout references input stage rdel delay inv-out out1 out2 3.15v + - vgate1 source iload load load supply ref input cdel 100nf select com ref input 100nf supply uv lockout references input stage rdel delay 5k w select com 100nf inv-out out1 out2 power & control 3.15v + - vgate2 cdel com power & control figure 6. master/slave synchronisation. figure 7. input to output delay circuitry. out1 out2 power & control c del ref input 1 00nf 100nf select s uppl y uv lockout references input st age r del out1 com out2 source 5k w vgate2 com lo ad h.v.bus iload vgate1 delay 3.15v + - power & control ref input 1 00nf suppl y uv lockout references input st age r del 5k w dela y 3.15v + - select c del AN556 application note 4/16
the relationship between the rc parts value and the internal timing circuitry is: t delay =r del c del [1] where: r del is the timing resistance [k w ] c del is the timing capacitance [ m f] t delay is the input to output delay time [ m s] t delay should be calibration on the difference in response time of the external parts (e.g. optocoupler, switch). the delay pin always needs a pull-up resistor. protection against failure to avoid system damage, it is mandatory not to exceed the soa of the selected switch. to better under- stand how to respect these limits, the relationships describing the operating conditions of a voltage con- trolled switch are here reminded: is 9 0 vg < vth (off mode) [2a] is m vd vd < vg-vth (on mode) [2b] is m (vg-vth) 2 vd > vg-vth (linear mode) [2c] where : is is the current through the switch vd is the switch drop voltage vth is the activation threshold voltage vg is the driving gate voltage the [2a] states that the switch current is negligible as long as the gate voltage is under the activation threshold; the [2b] states that the on state voltage drop across a well driven switch is usually very low; the [2c] states that the voltage drop across a bad-working switch, is always higher. protection against steady-state switch overload the equations [2b] and [2c] suggest an easy way for a load failure detection by monitoring the switch voltage drop. the l6353 performs this function connecting the on-sense pin as shown fig.8. the func- tion is turned off by shorting this pin to com. the diode must be ultra-fast and have the same voltage rating as the external switch. a load failure is detected by comparing the sense voltage to a reference level. on failure detection, the l6353 turns off immediately (<400ns) the switch and sets the alarm low. the input falling edge resets the driver. for an improved versatility, the on-lev-prog pin allows to ref 100nf input select 100nf supply uv lockout references on-lev-prog + - r h out1 com out2 on-sense vcc 200 m a power & control r l iswitch vdrop-switch vgate figure 8. load failure protection AN556 application note 5/16
change (by means of a resistive divider) the reference level from the default 7.5v, in the range 5v - 15v. the relationship between the reference level and the resistive divider (from ref pin) is: v on-lev-prog = 0.17 v on-sense [3a] v on-lev-prog = v ref r l r h + r l [3b] of course, v on-sense is the switch voltage drop (when it is carrying the overload current) plus a diode forward drop. the graph of fig. 9 helps design: you draw a line crossing the vl-p axis at v on-sense and read the resistor value on the other two axes. the divider is tuned by solving equations [3a] and [3b]. the example shows how to set the maximum drop voltage to 7v (+0.7v) using two resistors of 22k and 6.8k. safe turn-on of power switch on a low-impedance load if you turn on a switch connected to a low-impedance load (for example: a short circuit) by feeding the gate a full voltage then high switch currents will occur (see [2c]). in igbt's, such a current can be so high to fire the parasitic scr, which destroys the switch (latch-up). the l6353 avoids this risk with a safe turn-on procedure in two steps (see fig.10): on the first step it does not monitor the switch voltage drop but limits the switch current by clamping the gate voltage; on the second step it applies the full volt- age at switch gate while the voltage drop is monitored. the relationships between the gate clamped voltage and a resistive divider (from ref pin) is: v clamp-prog = 0.17 v clamp [4a] v clamp-prog = v ref r l r h + r l [4b] where: v clamp-prog is the clamp-prog pin voltage v clamp is the first step gate voltage v l_p r h r l 30 50 20 3 7 10 5 1 2 3 7 10 5 1 2 8 5 15 10 6 12 11 13 14 7 9 figure 9. level-proggraph t dela y t r vin vout1 vpos v clamp vss vga te vpos v clamp v mi ller vss t rr t miller t mo n_delay v th short circuit & overcurrent protected area vce/vds h.v . v ont h dv/dt v ondr op figure 10. power switch protection method AN556 application note 6/16
the following relationships provide the way to relate v clamp to the switch characteristics: v clamp =v miller +v ovr [4c] v miller =v th + i s0 g fm [4d] where: v miller is the gate voltage during miller's modulation of gate capacitance. v ovr is the miller's excess voltage for a fast turn-on g fm is the power switch transconductance i s0 is the nominal load current the graph of fig.11 helps find the resistors values: you draw a line crossing the vc-p axis at v clamp and read the resistors value on the other two axes. the divider is tuned by solving the equation [4a] and [4b]. the example shows how to set the gate-clamped voltage to 8v using resistors of 22k and 7.5k. in case the switch is a mos, which does not suffer from latch-up, then the function can be excluded by shorting the clamp-prog pin to com. delaying the monitor function fig.12 shows the characteristics of a typical voltage controlled switch. to reach the gate voltage needed for a full conduction of the switch, a certain amount of charge (de- pending both on the switch and the application) must be stored into the gate capacitance. since this is charged with a limited current source, the switch turn-on transition needs some time. this means that until transition is completed, the monitoring of the switch voltage drop must be blanked. the relation- ships between the blanking time and the rc cell (from ref pin) is: t mon-delay =r ext c ext [5a] where: t mon-delay is the monitoring signal blanking time [ m s] r ext is the timing resistance [k w ] c ext is the timing capacitance [ m f] v c_p r h r l 30 33 20 3 7 10 5 1.73 2 7 3 10 5 1 2 8 10 11 7 9 figure 11. clamp-prog graph 0 100 200 300 400 500 600 700 0 100 200 300 400 500 0 3 6 9 12 15 gate charge [nc] switch voltage-drop [v] gate voltage [v] figure 12. typical voltage controlled switch characteristics AN556 application note 7/16
on the other hand, the time to reach the true low voltage drop is the sum of the turn-on time, the transi- tion time of the switch at loading conditions and a margin time for the spread (limited only by the switch thermal performance), so: t mon-delay =t on +t miller +t mrg [5b] t on =r gon c i ln t y u v clamp - v ss v clamp - v miller n m < [5c] t miller = q miller - c i v miller v clamp - v miller r gon [5d] where: t on is the time to reach the gate voltage threshold t miller is the transition duration of switch voltage t mrg is a designer time margin q miller is the charge amount to go beyond the gate voltage plateau c i is the input gate capacitance r gon is the charging resistance r goff is the discharging resistance the mon-delay pin always needs a pull-up resistor. controlling the di/dt and the static dv/dt of external power a lot of problems in switching systems (emi, power switch latch-up, optocoupler short-circuit, etc.) are caused by high dv/dt and di/dt. it is easy to avoid these problems with the l6353 because the output buffer is split in high-side and low-side. in this way, only one pair of resistors is needed to shape both dv/dt at turn-off and di/dt at turn-on. fig.13 shows the connectionof the output pins and the switch gate. during the switch transition most of the charge flowing into the gate pin is used to balance the discharge of the reverse transfer capacitance. then, the gate voltage stops at a level which depends on load current and switch, while the gate driver is like a current source. it follows that transient duration can be approximated to charge and discharge time of this capacitance and the resistors in series to the gate input power & cont rol vcc vpos vss out1 r gon out2 r goff com 100 m f negat ivebi as posi ti ve suppl y vgate 100 m f iload vdrop-switch figure 13. typical connection between ic and the switch gate AN556 application note 8/16
can be designed with the relationships: dv dt j turn - on @ v out1 - v miller r gon c r [6a] di dt j turn - off @ g fm v ss - v th - i 2 g fm r goff c i [6b] where: t on is the duration of turn-on switch transition c i is the input capacitance c r is the reverse transfer capacitance r gon is the charging resistance r goff is the discharging resistance g fm is the transconductance of the external power driver supply the l6353 is provided with separated pins for its supply: one for control circuits (vcc) and two for the power circuits (v pos , vss). an undervoltage circuitry monitors the control circuits supply and ties out2 to vss as long as vcc voltage is under 11.5v, while the alarm is low. the power circuits positive pole (v pos ) can be connected to vcc. the negative pole (vss) is useful to increase the dv/dt latch-up im- munity of the switch by feeding a negative bias to its gate (up to -7v). if the negative bias is not required, vss can be connected to com. to supply the device it must be considered that a buffer capacitor is needed to sustain the current pulses absorbed by v pos at switch turn-on. the buffer capacitor must be designed considering the rms values of this pulsed current: i grms . / ````````` v pos v q gate v f sw 3r gon using the same considerations, the buffer capacitor on vss (if used) withstands the rms current that is: i grms . / ````````` vss v q gate v f sw 3r goff i/o logic com supply uv lockout references vcc 100 m f vpos vss out1 out2 100 m f negative bias positive supply 100nf figure 14. optimal supply AN556 application note 9/16
where: i rms is the capacitors rms current q gate is the total amount of gate charge v pos is the steady-state gate voltage vss is the negative supply voltage r gon/off are the gate resistance at turn-on and at turn-off f sw is the operating frequency thermal balance and frequency limitation the l6353 improves the system reliability integrating a circuit which monitors the chip temperature. there are a temperature sensor and a comparator stage with two very precise thresholds: at 130 5 c the chip sends the alarm signal but keeps on working and at 160 5 c shutdowns the output stage. it follows that a design with l6353 is easy because just few data allow to estimate the chip temperature: operating conditions, power dissipated and package thermal characteristic. t j =r th p d +t a [8a] p d =p q +p al +p inv +p sw [8b] p q =i q v cc +i ref (v cc -v ref ) p al =i al v drop d p inv =i inv v drop d psw = {[(vp os -v clamp )(q miller -v ss c i )+2(v pos -v out1 )(v pos -v out1 -v miller )c i + (v out2 -v ss )[v pos c i +q miller -v ss c i ]}f [8c] where: p d is the total power dissipated p q is the quiescent power dissipated in the chip p inv is the power dissipated using the inv-out function p al is the power dissipated using the alarm function p sw is the operative power dissipated during transition d is the switch duty-cycle r th is the package thermal resistance substituting into [7a] and rewriting: p sw 3 t j - t a r th - p q [8d] for the total gate charge of the switch, consid- ering the over heating alarm threshold and the available packages, the relationship [8d] states a limit of operating frequency (see fig.15). 10 100 1000 frequency [khz] 100 1000 max.gate-charge [nc] vcc =15v i alarm =3ma } no clamp } vclamp=10v } vclamp=5v dip16 so16 figure 15. maximum gate-charge vs operative AN556 application note 10/16
promotional tool for l6353 fig.16 shows a printed circuit board where it is possible to assembly one of the following circuits with possibility to try different set-ups: (optocoupler either open-collector with a pull-up resistor or totem-pole output needing 5v supply; a switch which can be either mosfet or igbt with a free-wheeling diode mounted on a heat-sink).for more complex configurations like inverter legs, bridge etc. two or more of them can be connected together. the pcb has also the aim to introduce a few layout rules to avoid interference and parasitic effects which arise switching high current. firstly, on single-supply driving, a minimal track length between vss and com pins is mandatory. on the supply tracks, the capacitor location is very close to the ic pins. the pin com must be connected near the supply capacitor. it is necessary to take special care of the switch pin used for both power and control, which is connected to the supply capacitor by a separated, wide and short track. finally, a ground track must be put under each optocoupler to improve its dv/dt im- munity. figure 16. printed circuit board (scale 1:1) AN556 application note 11/16
since it can be used stand-alone, there is an excess of parts: the supply circuitry (the rectifier bridges, zeners and limiting resistors) is designed to feed a floating double polarity connecting only a transformer; the control source is coupled with an optocoupler; the clamped gate-voltage and the maximum voltage drop allowed across the switch can be trimmed at values that are best matching the switch characteristic (either default or otherwise); two led connected to the alarm that are exclusively brightening to indicate the board status: either normal or fault; two led connected to the inv-out (just to show the signal). in fig. 18, a typical application circuit, pruned of the parts in excess, is shown. 3 2 ic 1 l6353 4 clamp-prog delay r 10 c 10 10 on-lev-prog 12 mon-delay ref r 7 c 7 7 ref d 13 r 1 r 16 on-sense 13 15 out2 out1 1 16 com q select 5 6 d 61 r 61 d 62 j 2 vpos vcc inv-out alarm r 62 d 51 r 51 d 52 j 1 r 52 c 8 9 input r 82 ic 2 r 20 signal sourc e 11 c 11 j 3 c 12 r 12 ref r 82 c 4 r 4 ref r 81 c 3 +vp ~+ ~- r 3 dz 1 ic 3 -vn ref 8 c 14 vss 14 c 15 r 14 dz 2 ic 4 ~- ~+ figure 17. test-circuit schematic. parts list ic1 = l6353 ic2 = 4n25 ic3 = bridge rectifier ic4 = bridge rectifier d1 = byt11-1000 d51 = yellow led d52 = yellow led d61 = red led d62 = green led dz1 = bzx85c6v8 dz2 = bzx85c20 r1 = 1.2 w - 1w (metal) r3 = 10 w -0.5w (metal) r61 = 10k w -.25w r7 = 4.7k w -.25w -1% r10 =4.7k w -.25w - 1% r14 = 100 w -0.5w (metal r16 = 5.6 w - 1w (metal) r20 = 470 w -.25w r80 =4.7k w -.25w r81 = 4.7k w -.25w r82 = 4.7k w -.25w c3 = 100 m f-25v (low esr) c4 =100nf (multi) c7 = 1nf (multi) c8 = 4.7nf (multi) c10 = 1nf (multi) c12 =100nf (multi) c14 =100 m f- 25v(low esr) q = stw20na50 * d 61 r 61 d 13 on-sense 13 3 inv-out 6 alarm 5 vpos 2 15 vcc r 1 r 16 out2 out1 1 16 c 3 com ic 1 l6353 14 ref +vp vss c 14 -vn ic 2 r 20 9 input r 82 ref signal source q delay r 10 c 10 10 12 on-lev-prog c 4 4 clamp-prog c 12 r 7 c 7 7 mon-delay ref ref select 11 c 8 8 figure 18. typical application schematic. AN556 application note 12/16
application suggestions - extension of inv-out the switch immunity against static dv/dt is weakened by requirements of single supply or slow turn-off. an improvement is made by tieing, at turn-off, the gate to the common pin of theswitch. this is easily im- plemented by the inv-out pin with a cheap additional circuit: a small bjt, a capacitor and a resistor with a diode in parallel to speed-up the bjt turn-off. the bjt does not have to carry the gate discharge current, so it can be of a small size. fig.19 shows a practical example of its usage: - soft turn-off in any switch overload conditions fig.20 shows a simple circuit which implements this function; the waveforms show both the high voltage overshoot if you use the normal switch-off speed on load short-circuit and the short voltage overshoot if you use the soft turn-off. the typical off resistor values are in the range of the same hundreds ohm in osoft turn-offo and up to some tens ohm in normal switch-off. source to load 47 w input power & control com vss out1 r gon out2 r goff load power supply inv-out select 100nf com 47 w input power & control com vss out1 r gon out2 r goff inv-out select 100nf com figure 19. improved dv/dt immunity on single supply AN556 application note 13/16
- first failure hold-off with external reset fig.21 shows a simple circuit which holds in off state the switch after the first failure alarm. on switch failure (eg. an overload), the alarm disables the input control signal and the driver normal operation is resumed by a low level pulse on reset. from load com vss out1 r gon out2 r goff alarm 1/2 m74hc279 reset from m p bzx85c4v7 input select 100nf delay source 1nf 4 . 7 k w 100nf vref power & control byt11 1000 von-sense 47 w r s 22k w x-alarm q figure 21. first failure hold-off with external reset circuit to com vss out1 alarm input com r gon out2 r goff r soft power & control 5.6nf 56nf 2.2k w 2 . 2 k w std12n06 iswitch vswitch figure 20. soft turn off circuit and waveforms std8n06 AN556 application note 14/16
- an inverter leg fig.22 shows a leg of an inverter and also highlights how you need few parts for its construction. of course, to test this circuit two demo-pcb, linked side-by-side, can be used. the two boards joining point is the middle of the leg, which is connected to the load, and the remaining two are connected to the load power supply. references: 1. r. letor -a brief look at static dv/dt in power mosfets- sgs thomson microelectronics -application note, tn197/0688 2. s.musumeci et al..-a new adaptive driving technique for high current gate controlled devices- ieee apec'94 - feb.13-17,1994- orlando fl (usa) - pp.480-486. 3. c.licitra et al. -a new driving circuit for igbt devices- ieee transactions on power electronics, may'95 4. t.hopkins et al. -designing with thermal impedance- sgs thomson microelectronics - application note, an261 d 61 r 61 d 13 on-sense 13 3 inv-out 6 alarm 5 vpos 2 15 vcc r 1 r 16 out2 out1 1 16 c 3 com ic 1 l6353 14 ref 8 c 8 +vp ref vss c 14 -vn ic 2 r 20 input 9 r 82 signal source q delay r 10 c 10 10 12 on-lev-prog c 4 4 clamp-prog c 12 r 7 c 7 7 mon-delay ref ref select 11 c 11 d 61 r 61 d 13 on-sense 13 3 inv-out 6 alarm 5 vpos 2 15 vcc r 1 r 16 out2 out1 1 16 c 3 com ic 1 l6353 14 ref +vp vss c 14 -vn ic 2 r 20 9 input r 82 ref signal source q delay r 10 c 10 10 12 on-lev-prog c 4 4 clamp-prog c 12 r 7 c 7 7 mon-delay ref ref select 11 c 8 8 output ( to load) load powersupply figure 22. inverter-leg. AN556 application note 15/16
information furnished is believed to be accurate and reliable. however, sgs-thomson microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of sgs-thomson microelectronics. specification men- tioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. sgs-thomson microelectronics products are not authorized for use as critical components in life support devices or systems without ex- press written approval of sgs-thomson microelectronics. { 1997 sgs-thomson microelectronics printed in italy all rights reserved sgs-thomson microelectronics group of companies australia - brazil - canada - china - france - germany - hong kong - italy - japan - korea - malaysia - malta - morocco - the netherlands - singapore - spain - sweden - switzerland - taiwan - thailand - united kingdom - u.s.a. AN556 application note 16/16

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